Nano-fabrication involves the fabrication of very small structures, e.g., having features on the order of nanometers or smaller. One area in which nano-fabrication has had a sizeable impact is in the processing of integrated circuits. As the semiconductor processing industry continues to strive for larger production yields while increasing the circuits per unit area formed on a substrate, nano-fabrication becomes increasingly important. Nano-fabrication provides greater process control while allowing increased reduction of the minimum feature dimension of the structures formed. Other areas of development in which nano-fabrication has been employed include biotechnology, optical technology, mechanical systems and the like.
An exemplary nano-fabrication technique is commonly referred to as imprint lithography. Exemplary imprint lithography processes are described in detail in numerous publications, such as U.S. patent application publication 2004/0065976 filed as U.S. patent application Ser. No. 10/264,960, entitled, “Method and a Mold to Arrange Features on a Substrate to Replicate Features having Minimal Dimensional Variability”; U.S. patent application publication 2004/0065252 filed as U.S. patent application Ser. No. 10/264,926, entitled “Method of Forming a Layer on a Substrate to Facilitate Fabrication of Metrology Standards”; and U.S. Pat. No. 6,936,194, entitled “Functional Patterning Material for Imprint Lithography Processes,” all of which are assigned to the assignee of the present invention.
Imprint lithography disclosed in each of the aforementioned U.S. patent application publications and U.S. patent includes formation of a relief pattern in a polymerizable layer and transferring a pattern corresponding to the relief pattern into an underlying substrate. The substrate may be positioned upon a motion stage to obtain a desired position to facilitate patterning thereof. To that end, a template is employed spaced-apart from the substrate with a formable liquid present between the template and the substrate. The liquid is solidified to form a solidified layer that has a pattern recorded therein that is conforming to a shape of the surface of the template in contact with the liquid. The template is then separated from the solidified layer such that the template and the substrate are spaced-apart. The substrate and the solidified layer are then subjected to processes to transfer, into the substrate, a relief image that corresponds to the pattern in the solidified layer.
The solidified layer may comprise a residual layer of material, i.e., a contiguous layer. Residual layer thickness (RLT) and residual layer thickness uniformity are key metrics for evaluating the quality of imprinted wafers. For many applications, a plasma etch step directly follows imprinting. Film thickness uniformity requirements for plasma etching are well known in the field. RLT uniformity determines the film thickness uniformity of imprinted samples to be etched. Presently, residual layer thickness uniformity is evaluated using the unaided eye to look at fringe patterns. To that end, there is no quantitative feedback to improve the residual layer uniformity once the liquid is positioned between the template and the substrate.